Few examples on Verilog assignment If you refer to v2005 LRM, there are 2 interesting definitions, an extract of which is pasted below – 6.1 Continuous assignments Drives values onto nets, both vector and scalar; this assignment shall occur whenever the value of the right-hand side changes. An example is below: assign a = b; …
Hi Folks, This is a longish read. I am covering reg and integer keywords of Verilog. These two topics are quite huge, but I have summarized the most used ways here. I suggest that you type and practice to ascertain yourselves as you read. If you have any questions, put them below in the comment …
Hi Folks In the last write-up, I mentioned threads in simulation. Specifically, I said that the threads of a simulation can interact with each other. Well, what does that mean? Consider the Verilog code-snippet below – assign y = a + b; // continuous assignment initial begin // initial block $monitor(“@time %t -> a=%d, b=%d, …
Hi Folks, In the last writing, I used a phrase — ‘procedural block’. Most of you know what it means in Verilog. Actually, there is no need to write about it here, but I just thought of organizing the write-ups a bit and hence this article. So, here is a quick intro. In fact, in …
Hi folks, As we prepare ourselves to launch our first blog on hardware modeling using Verilog, we think it is better to give this preamble. Yes, we use Verilog to model hardware. Actually, we use it to model the behavior of a system. In our 2 decades of experience with colleagues new to Verilog, we …
Hi Folks, Among the list of articles we have at hand, our team kept wondering what could be a good first article. As such, we have quite an ambitious list split into 3 streams – 1. Digital design & verification using HVL and HDL 2. OOPs 3. CAD Each stream has ready blogs that last …
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