We need engineers from across all experience levels from entry level fresh graduates to technical leaders.
What we look for in our leads is specifically an ability to build and propagate a culture which is empathetic, committed and ambitious. We expect our leaders to shoulder great responsibilities not only in project execution, but also in shaping the career of their team members and guide them to become valuable assets to the industry and the society in general. Our leaders are required to possess a great deal of social responsibility and also have to show a go-getter attitude in project delivery assignments.
What we look for, generally in all our lead role applicants is that they –
- Should have experience in working with and providing guidance to new college graduates.
- Should have a flair for team-building.
- Should possess good leadership skills with good communication and human interface.
- Should exhibit maturity and patience in handling difficulty in project situations and manage human relationships well to avoid conflicts and bring about efficient execution.
Of course, Proxelera management and HR is available at all times to help you in these matters. As a lead, you have to sense when you need help and get in touch with relevant people – and we promise to work together.
EXPLORE CURRENT OPENINGS
- At least 4 years of experience in complex IPs or SoCs.
- Good knowledge in SystemVerilog, UVM, C/C++ test writing
- Constrained random or directed testing experience in achieving functional and code coverage closure
- At least one project tape-out experience, preferably with exposure to functional issues from the field usage and replicating them in RTL testing
- Desirable to have experience in mentoring a couple of junior engineers
- At least 8 years of experience in verification of complex IPs, subsystems, ASICs or SoCs
- Should possess deep knowledge of SystemVerilog with UVM or similar className library, SoC level C/C++ tests and infrastructure
- Should have a proven track record of working in multiple projects in all areas of verification including test planning, coverage definition, test bench creation, regression, report generation and sign-off
- Should be able to partition verification work into multiple independent units, assign them to engineers, provide guidance and deliver with quality and timeliness
- At least 8 years of experience in RTL design at both IP level and SoC/ASIC integration levels
- Complete project participation experience in at least 1 high speed serial interface project, preferably at IP level
- Should come with good design practice and ability to put-together design and coding guidelines
- Should possess good leadership skills with good communication and human interface
- Should have at least 8 years of experience in RTL design/integration, synthesis and static timing analysis
- Should have a good knowledge of industry leading synthesis and STA tools. Should have prior working experience at both IP and full-chip levels and should have supported in tape-out activities
- Should have experience in pre-layout and post-layout timing analysis and should have experience in working closely with physical design teams to achieve timing closure
- Should have good scripting abilities (PERL/TCL) and should have experience in setting up synthesis and STA flows from scratch
- Hands-on work experience of at least 8 years, with project track record in advanced nodes upto 5nm
- Deep expertise of industry leading place and route, PV and other physical design tools
- Experience in working in full chip or at block level, owning complete delivery responsibilities of a team of at least 12-15 engineers
- Experience in floorplan, placement, place & route and physical verification
- Coordination experience with logic design and synthesis team to resolve power, area and timing related issues to provide best results to customers
- Good exposure to issues and solution in electrical issues of latest geometry nodes in VLSI
INFORMATION
CONTACT US
PROXELERA
R&D – Bangalore:
Ground Floor, Datta Prabhasm 3rd Phase, No.44/A, 1st Main Rd, next to MTR Grand, Mini Forest Area, Sarakki Industrial Layout, 3rd Phase, J. P. Nagar, Bengaluru 560078
R&D – Mysuru:
Regd. Office: 002, Skyline Chalet, 2/1-12, OVH Road, Basavanagudi, Bangalore 560004
Contact Us: careers@proxelera.com